Module 2 — assert / assume / cover

The three SVA primitives that control every proof. Meet the vacuous PASS, learn why an over-constrained assume hides real bugs, and use cover to find unreachable states.

Katas in this module (3)

• Kata 2.1 — The Vacuous PASS
• Kata 2.2 — Write assume and assert Together
• Kata 2.3 — Use cover to Find an Unreachable State

Part of Hardware Formal Verification on formal.org.