Module 10 — Capstone

Assemble a full AXI4-Lite register-bank property suite, catch two independent bugs with it, and prove a corrected design under mode prove.

Katas in this module (3)

• Kata 10.1 — R Channel Stability
• Kata 10.2 — Full Register Bank
• Kata 10.3 — Prove the Fix

Part of Hardware Formal Verification on formal.org.